3.3.3 Karnaugh Maps

In computers, parallel processing is the processing of program instructions by dividing them among multiple processors with the objective of running a program in less time.In other words it is  the simultaneous use of several  processors to perform a single job Four basic computer  architectures are  $ single instruction, single data  (SISD),   $ single instruction, multiple data  (SIMD),  $ multiple instruction, single data  (MISD),  $ multiple instruction, multiple data  (MIMD) Single instruction, single data  (SISD) @    A computer that does not have the ability for parallel processing @ There is only one processor executing one set of instructions on a single set of data.   Single instruction, multiple data  (SIMD) @  The processor has several ALUs. Each ALU executes the same instruction but on different data. Multiple instruction, single data  (MISD) Multiple instru...

                                                 User Defined Data Types A user-defined data type (UDT) is a data type that derived from an existing data type. You can use UDTs to extend the built-in types already available and create your own customized data types. Non composite Data Type : Single data type not involving reference to any other data type          Now please note that first four are non composite and in built data types whereas pointer and enumerated data types are non composite and user defined data types * Integer  ( Whole numbers ) * Real ( Decimal Numbers ) * String (Alphanumeric Data ) * Boolean ( True/False ) * Pointer ( Number used to reference a memory location ) * Enumerated ( A list of possible data values ) Enumerated  Pseudocode : TYPE             ...

Differences   :  RISC Vs CISC • RISC has fewer instructions // CISC has more instructions • RISC has many registers // CISC has few registers • RISCs instructions are simpler  // CISC’s instructions are more complex • RISC has a few instruction formats // CISC has many instruction formats • RISC usually uses single-cycle instructions // CISC uses multi-cycle instructions • RISC uses fixed-length instructions  // CISC uses variable-length instructions • RISC has better pipelineability  // CISC has poorer pipelineability • RISC requires less complex circuits // CISC requires more complex circuits • RISC has fewer addressing modes  // CISC has more addressing modes • RISC makes more use of RAM // CISC makes more use of cache/less use of RAM • RISC has a hard-wired control unit  // CISC has a programmable control unit • RISC only uses load and store instructions to address memory  // CISC has many types of instructions to address memo...